In Serializer/Deserializer (SerDes) systems, on-chip AC (alternating current) capacitance is typically used to mitigate mismatches in differential signaling. This on-chip AC capacitance, or board capacitance, introduces distortion into the incoming signal at a receiver, which causes a baseline of the incoming signal to wander slowly. This impact can be viewed as a high-pass filtering of the incoming signal. The difference between the input to and the output of AC capacitance is called a baseline wander (BLW) signal.
The BLW signal can be viewed as a slowly varying voltage offset. To mitigate the effect of BLW on the incoming signal, a correction signal can be generated locally at the receiver and subtracted from the signal after on-chip AC capacitance or board capacitance. To generate such a BLW correction signal, a running disparity of decoded bits is passed through a low-pass filter whose cut-off frequency is the same as a cut-off frequency of the high-pass filtering because of AC capacitance and the output of low-pass filter is multiplied by the direct current (dc) gain of the system up to the receiver input. This BLW gain is approximately equal to the dc gain of the system up to the receiver input; i.e., the product of channel dc gain and transmitter (TX) dc gain. The strength of the BLW signal depends on the amount of disparity between 1's and 0's in the pattern and dc gain of the system up to the receiver input. When applications using the SerDes system recommend patterns that do not have sufficient randomness (e.g., patterns with a large running disparity of 1's and 0's), then there is a degradation in the performance of the SerDes system without BLW correction at the receiver. To avoid the degradation of performance, the correction of BLW distortion needs to be compensated at the receiver.
To estimate the dc gain at the receiver, digital least means square (LMS) gradients can be used based on minimum mean squared error between correction signal and BLW signal. This requires sampling of the incoming signal at the receiver front end. Because of the implementation constraints, obtaining such incoming signal sample at the receiver input is difficult. Approximations to avoid the use of such incoming signal samples in the gradient calculation are sub-optimal and have impact on the performance of SerDes system. The BLW gain is manually set to avoid all these problems in typical SerDes cores. Such manual setting is also difficult because TX dc gain and channel dc gain are not known in advance.